{"product_id":"mitsubishi-electric-a2acpup21-melsec-a-series-data-link-cpu-unit","title":"A2ACPUP21 | Mitsubishi Electric | Unité CPU liaison de données A 2 ACPUP 21","description":"\u003ch3\u003eDescription\u003c\/h3\u003e\n\u003cp style=\"color: #2d3748; margin-bottom: 1rem;\"\u003eIntegrating advanced optical network connectivity directly into the processor architecture, the \u003cstrong\u003eMitsubishi Electric A2ACPUP21\u003c\/strong\u003e serves as a specialized central processing unit for the legacy MELSEC A Series PLC platform. This module combines the processing performance of an \u003cstrong\u003eA2ACPU\u003c\/strong\u003e core with an integrated \u003cstrong\u003eMELSECNET optical data link\u003c\/strong\u003e interface, providing high-speed peer-to-peer and master-sub station communications across fiber-optic loops. By consolidating control execution and optical networking capabilities onto a single slot, this CPU unit optimizes backplane space efficiency and minimizes communication latency within distributed control topologies.\u003c\/p\u003e\n\n\u003ch3 style=\"color: #1a365d; margin-top: 1.5rem; margin-bottom: 0.5rem;\"\u003eKey Features\u003c\/h3\u003e\n\u003cul style=\"list-style-type: square; color: #2d3748; margin-bottom: 1.5rem; padding-left: 1.5rem;\"\u003e\n  \u003cli\u003e\n\u003cstrong\u003eIntegrated Optical Interface:\u003c\/strong\u003e Eliminates the need for a separate network module by building MELSECNET optical loop capabilities directly into the CPU.\u003c\/li\u003e\n  \u003cli\u003e\n\u003cstrong\u003eAdvanced Instruction Processing:\u003c\/strong\u003e High-speed execution of logic, sequence, and data manipulation instructions native to the A-Series controller range.\u003c\/li\u003e\n  \u003cli\u003e\n\u003cstrong\u003eNoise-Immune Communication:\u003c\/strong\u003e Fiber-optic transmission path provides absolute immunity to electromagnetic interference (EMI) and radio frequency interference (RFI) in harsh environments.\u003c\/li\u003e\n  \u003cli\u003e\n\u003cstrong\u003eDual-Loop Redundancy:\u003c\/strong\u003e Supports optical loop configurations to ensure uninterrupted communications in the event of a single cable breakage.\u003c\/li\u003e\n\u003c\/ul\u003e\n\n\u003ch3 style=\"color: #1a365d; margin-top: 1.5rem; margin-bottom: 0.5rem;\"\u003eApplications\u003c\/h3\u003e\n\u003cul style=\"list-style-type: square; color: #2d3748; margin-bottom: 1.5rem; padding-left: 1.5rem;\"\u003e\n  \u003cli\u003eAutomotive assembly line synchronization over distributed networks.\u003c\/li\u003e\n  \u003cli\u003eMunicipal water treatment facilities requiring isolated, long-distance inter-station communication.\u003c\/li\u003e\n  \u003cli\u003eHeavy metallurgical processing plants with high EMI\/RFI electrical noise profiles.\u003c\/li\u003e\n  \u003cli\u003eLarge-scale material handling and conveyor network control architectures.\u003c\/li\u003e\n\u003c\/ul\u003e\n\n\u003ch3 style=\"color: #1a365d; margin-top: 1.5rem; margin-bottom: 0.5rem;\"\u003eTechnical Specifications\u003c\/h3\u003e\n\u003cdiv style=\"overflow-x: auto; width: 100%; margin-bottom: 1.5rem;\"\u003e\n  \u003ctable style=\"border-collapse: collapse; width: 100%; color: #2d3748;\"\u003e\n    \u003ctbody\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 0.75rem; font-weight: bold; width: 30%;\"\u003eManufacturer\u003c\/td\u003e\n        \u003ctd style=\"padding: 0.75rem;\"\u003eMitsubishi Electric\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 0.75rem; font-weight: bold;\"\u003eModel Number\u003c\/td\u003e\n        \u003ctd style=\"padding: 0.75rem;\"\u003eA2ACPUP21\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 0.75rem; font-weight: bold;\"\u003eProduct Line\u003c\/td\u003e\n        \u003ctd style=\"padding: 0.75rem;\"\u003eMELSEC A Series\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 0.75rem; font-weight: bold;\"\u003eModule Type\u003c\/td\u003e\n        \u003ctd style=\"padding: 0.75rem;\"\u003eData Link PLC CPU Unit\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 0.75rem; font-weight: bold;\"\u003eNetwork Interface\u003c\/td\u003e\n        \u003ctd style=\"padding: 0.75rem;\"\u003eMELSECNET Optical Fiber Loop (P21 Type)\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 0.75rem; font-weight: bold;\"\u003eMedium Link Connection\u003c\/td\u003e\n        \u003ctd style=\"padding: 0.75rem;\"\u003eDual-core optical fiber cable (SI\/GI spec)\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 0.75rem; font-weight: bold;\"\u003eOperating Temperature\u003c\/td\u003e\n        \u003ctd style=\"padding: 0.75rem;\"\u003e0 to 55 degC\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 0.75rem; font-weight: bold;\"\u003eCountry of Origin\u003c\/td\u003e\n        \u003ctd style=\"padding: 0.75rem;\"\u003eJapan\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 0.75rem; font-weight: bold;\"\u003eShipping Weight (Calculated)\u003c\/td\u003e\n        \u003ctd style=\"padding: 0.75rem;\"\u003e2.0 kg (4.41 lbs)\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 0.75rem; font-weight: bold;\"\u003ePackage Dimensions (Calculated)\u003c\/td\u003e\n        \u003ctd style=\"padding: 0.75rem;\"\u003e250 mm x 110 mm x 130 mm\u003c\/td\u003e\n      \u003c\/tr\u003e\n    \u003c\/tbody\u003e\n  \u003c\/table\u003e\n\u003c\/div\u003e\n\n\u003ch3 style=\"color: #1a365d; margin-top: 1.5rem; margin-bottom: 0.5rem;\"\u003eOptical Connections and Interfaces\u003c\/h3\u003e\n\u003cdiv style=\"overflow-x: auto; width: 100%; margin-bottom: 1.5rem;\"\u003e\n  \u003ctable style=\"border-collapse: collapse; width: 100%; color: #2d3748;\"\u003e\n    \u003cthead\u003e\n      \u003ctr style=\"border-bottom: 2px solid #cbd5e0;\"\u003e\n        \u003cth style=\"text-align: left; padding: 0.75rem; font-weight: bold;\"\u003ePort \/ Interface\u003c\/th\u003e\n        \u003cth style=\"text-align: left; padding: 0.75rem; font-weight: bold;\"\u003eFunction \/ Cable Assignment\u003c\/th\u003e\n      \u003c\/tr\u003e\n    \u003c\/thead\u003e\n    \u003ctbody\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 0.75rem; font-weight: bold;\"\u003eTX Port\u003c\/td\u003e\n        \u003ctd style=\"padding: 0.75rem;\"\u003eOptical fiber transmitter (outbound loop segment)\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 0.75rem; font-weight: bold;\"\u003eRX Port\u003c\/td\u003e\n        \u003ctd style=\"padding: 0.75rem;\"\u003eOptical fiber receiver (inbound loop segment)\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 0.75rem; font-weight: bold;\"\u003eRS-232C Port\u003c\/td\u003e\n        \u003ctd style=\"padding: 0.75rem;\"\u003eProgramming, debugging, and peripheral connectivity interface\u003c\/td\u003e\n      \u003c\/tr\u003e\n    \u003c\/tbody\u003e\n  \u003c\/table\u003e\n\u003c\/div\u003e\n\n\u003ch3 style=\"color: #1a365d; margin-top: 1.5rem; margin-bottom: 0.5rem;\"\u003eEmpirical Engineering Insights\u003c\/h3\u003e\n\n\u003ch4 style=\"color: #2b6cb0; margin-top: 1rem; margin-bottom: 0.5rem;\"\u003eAlternative Models \u0026amp; Compatibility\u003c\/h4\u003e\n\u003cp style=\"color: #2d3748; margin-bottom: 1rem;\"\u003eThe A2ACPUP21 integrates functions equivalent to an A2ACPU combined with an AJ71LP21 optical data link card. When replacing older non-integrated configurations, ensure your program address allocations accommodate the integrated link parameters. Be aware that the optical transceiver circuits are optimized for SI-type (plastic-clad) or GI-type (glass) fiber optic cables; matching the correct cable attenuation characteristics is critical for link stability.\u003c\/p\u003e\n\n\u003ch4 style=\"color: #2b6cb0; margin-top: 1rem; margin-bottom: 0.5rem;\"\u003eApplication Pitfalls \u0026amp; Engineering Notes\u003c\/h4\u003e\n\u003cp style=\"color: #2d3748; margin-bottom: 1rem;\"\u003eA common field issue with legacy MELSECNET optical modules is signal degradation caused by micro-bends or dust accumulation inside the fiber ports. Ensure you maintain the manufacturer's specified minimum bend radius for the fiber cables inside the wiring duct. Always use standard protective dust caps on unused RX\/TX channels to prevent contamination of the optical transceiver lenses.\u003c\/p\u003e\n\n\u003ch4 style=\"color: #2b6cb0; margin-top: 1rem; margin-bottom: 0.5rem;\"\u003eCommissioning \u0026amp; Wiring Tips\u003c\/h4\u003e\n\u003cp style=\"color: #2d3748; margin-bottom: 1rem;\"\u003eDuring initial commissioning, verify the station number and network settings using the hardware rotary switches located on the front faceplate of the CPU prior to powering up the chassis. If the \"L.ERR\" (Link Error) LED activates, verify that the TX of the master station is connected directly to the RX of the local station. Interchanging the TX\/RX fiber connections is the leading cause of initial handshake failures in redundant optical loop configurations.\u003c\/p\u003e\n\n\u003ch3 style=\"color: #1a365d; margin-top: 1.5rem; margin-bottom: 0.5rem;\"\u003eInstallation Guidelines\u003c\/h3\u003e\n\u003cdiv style=\"background-color: #fff5f5; border-left: 4px solid #c53030; padding: 1rem; margin-bottom: 1.5rem;\"\u003e\n  \u003cp style=\"color: #9b2c2c; font-weight: bold; margin: 0 0 0.5rem 0;\"\u003eCRITICAL WARNING\u003c\/p\u003e\n  \u003cp style=\"color: #9b2c2c; margin: 0;\"\u003eIsolate and lock out all AC\/DC power sources feeding the PLC backplane chassis before installing, removing, or adjusting the CPU unit. Failure to completely de-energize the system can result in electrical shock, hardware destruction, or erratic control system behaviors that could lead to machinery damage.\u003c\/p\u003e\n\u003c\/div\u003e\n\n\u003cdiv style=\"display: flex; flex-direction: column; gap: 1rem; margin-bottom: 1.5rem;\"\u003e\n  \u003cdiv style=\"display: flex; align-items: flex-start; gap: 1rem;\"\u003e\n    \u003cdiv style=\"background-color: #2b6cb0; color: #ffffff; width: 28px; height: 28px; border-radius: 50%; display: flex; align-items: center; justify-content: center; font-weight: bold; flex-shrink: 0;\"\u003e1\u003c\/div\u003e\n    \u003cdiv style=\"color: #2d3748;\"\u003eEnsure the main chassis base unit is securely mounted and the system power supply module is fully de-energized.\u003c\/div\u003e\n  \u003c\/div\u003e\n  \u003cdiv style=\"display: flex; align-items: flex-start; gap: 1rem;\"\u003e\n    \u003cdiv style=\"background-color: #2b6cb0; color: #ffffff; width: 28px; height: 28px; border-radius: 50%; display: flex; align-items: center; justify-content: center; font-weight: bold; flex-shrink: 0;\"\u003e2\u003c\/div\u003e\n    \u003cdiv style=\"color: #2d3748;\"\u003eAlign the bottom retention hook of the A2ACPUP21 CPU module with the base unit guide slot, then pivot the module firmly into the backplane connector.\u003c\/div\u003e\n  \u003c\/div\u003e\n  \u003cdiv style=\"display: flex; align-items: flex-start; gap: 1rem;\"\u003e\n    \u003cdiv style=\"background-color: #2b6cb0; color: #ffffff; width: 28px; height: 28px; border-radius: 50%; display: flex; align-items: center; justify-content: center; font-weight: bold; flex-shrink: 0;\"\u003e3\u003c\/div\u003e\n    \u003cdiv style=\"color: #2d3748;\"\u003eSecure the module retention screw at the top of the unit to ensure mechanical stability against industrial vibrations.\u003c\/div\u003e\n  \u003c\/div\u003e\n  \u003cdiv style=\"display: flex; align-items: flex-start; gap: 1rem;\"\u003e\n    \u003cdiv style=\"background-color: #2b6cb0; color: #ffffff; width: 28px; height: 28px; border-radius: 50%; display: flex; align-items: center; justify-content: center; font-weight: bold; flex-shrink: 0;\"\u003e4\u003c\/div\u003e\n    \u003cdiv style=\"color: #2d3748;\"\u003eConnect the dual optical fiber loops to the RX and TX ports, ensuring proper latching alignment, and secure the peripheral RS-232C programming line.\u003c\/div\u003e\n  \u003c\/div\u003e\n\u003c\/div\u003e","brand":"Mitsubishi Electric","offers":[{"title":"Default Title","offer_id":53102131151211,"sku":"A2ACPUP21","price":100.0,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0953\/3227\/0443\/files\/A2ACPUP21-51xi3ofjt14.png?v=1776137189","url":"https:\/\/www.plcprotech.com\/fr\/products\/mitsubishi-electric-a2acpup21-melsec-a-series-data-link-cpu-unit","provider":"PLC ProTech Ltd.","version":"1.0","type":"link"}