{"product_id":"abb-stromberg-mem86-3x192k-programmable-memory-board","title":"ABB Stromberg MEM86-3X192K Programmable Memory Board","description":"\u003ch3\u003eProduct Overview\u003c\/h3\u003e\n\u003cp\u003eThe\u003cspan\u003e \u003c\/span\u003e\u003cstrong\u003eMEM86-3X192K (MEM86-3*192K)\u003c\/strong\u003e\u003cspan\u003e \u003c\/span\u003eis a high-density, general-purpose memory board designed specifically for the Allen-Bradley\/Stromberg Digital Reference Controller (DRC) rack systems. Engineered to consolidate hardware footprints, a single\u003cspan\u003e \u003c\/span\u003e\u003cstrong\u003eMEM86-3X192K\u003c\/strong\u003e\u003cspan\u003e \u003c\/span\u003ereplaces up to three independent MEM86-192K legacy boards. This module provides a highly flexible architecture, supporting a hybrid mix of 32 Kbyte EPROMs for firmware, CMOS-type Static RAM (SRAM) for high-speed program storage, and EEPROMs for non-volatile program backup. By integrating Command Line Interpreter (CLIM) and Block Memory (BLKM) functionalities onto a single PCB, it optimizes rack space while enhancing the data processing reliability of high-performance motor drives and industrial control systems.\u003c\/p\u003e\n\u003ch3\u003eTechnical Specifications\u003c\/h3\u003e\n\u003ctable\u003e\n\u003cthead\u003e\n\u003ctr class=\"firstRow\"\u003e\n\u003ctd\u003e\u003cstrong\u003eAttribute\u003c\/strong\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cstrong\u003eSpecification\u003c\/strong\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003c\/thead\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cspan\u003e\u003cstrong\u003eModel\u003c\/strong\u003e\u003c\/span\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cspan\u003eMEM86-3X192K (3100-MEM)\u003c\/span\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cspan\u003e\u003cstrong\u003eBrand\u003c\/strong\u003e\u003c\/span\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cspan\u003eABB \/ Stromberg (Allen-Bradley compatible)\u003c\/span\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cspan\u003e\u003cstrong\u003eTotal Memory Capacity\u003c\/strong\u003e\u003c\/span\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cspan\u003eUp to 576 Kbytes (3 x 192 Kbytes)\u003c\/span\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cspan\u003e\u003cstrong\u003eMemory Types Supported\u003c\/strong\u003e\u003c\/span\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cspan\u003eEPROM (27256), SRAM (62256), EEPROM (28256)\u003c\/span\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cspan\u003e\u003cstrong\u003eMemory Mapping\u003c\/strong\u003e\u003c\/span\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cspan\u003e18 individually software-mapped 32 Kbyte groups\u003c\/span\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cspan\u003e\u003cstrong\u003eWord Length\u003c\/strong\u003e\u003c\/span\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cspan\u003e16-bit (requires circuit pairs per mapped area)\u003c\/span\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cspan\u003e\u003cstrong\u003ePower Consumption (Basic)\u003c\/strong\u003e\u003c\/span\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cspan\u003e+5 VDC @ 1.2 A (Typical for MS4 configuration)\u003c\/span\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cspan\u003e\u003cstrong\u003eBackup Battery\u003c\/strong\u003e\u003c\/span\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cspan\u003eVarta 100 DKO, 3.6 V, 100 mAH (Ni-Cd)\u003c\/span\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cspan\u003e\u003cstrong\u003eOperating Temperature\u003c\/strong\u003e\u003c\/span\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cspan\u003e0 to 50 deg C\u003c\/span\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cspan\u003e\u003cstrong\u003eHumidity\u003c\/strong\u003e\u003c\/span\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cspan\u003e5 to 95% (non-condensing)\u003c\/span\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cspan\u003e\u003cstrong\u003eAddressing\u003c\/strong\u003e\u003c\/span\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cspan\u003e3 independent I\/O address areas via microswitches\u003c\/span\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003c\/tbody\u003e\n\u003c\/table\u003e\n\u003ch3\u003eFAQs\u003c\/h3\u003e\n\u003cp\u003e\u003cstrong\u003eWhat are the primary differences between the MS4, ME3, and MS5 configurations?\u003c\/strong\u003e\u003c\/p\u003e\n\u003cp\u003eThe\u003cspan\u003e \u003c\/span\u003e\u003cstrong\u003e3100-MS4\u003c\/strong\u003e\u003cspan\u003e \u003c\/span\u003eis the basic memory board equipped with CLIM and Block Memory firmware. The\u003cspan\u003e \u003c\/span\u003e\u003cstrong\u003e3100-ME3\u003c\/strong\u003e\u003cspan\u003e \u003c\/span\u003eserves strictly as a Backup Memory Board featuring high-capacity EEPROM storage. The\u003cspan\u003e \u003c\/span\u003e\u003cstrong\u003e3100-MS5\u003c\/strong\u003e\u003cspan\u003e \u003c\/span\u003eis a hybrid \"Basic + Backup\" solution that combines firmware execution with EEPROM redundancy for critical parameters.\u003c\/p\u003e\n\u003cp\u003e\u003cstrong\u003eHow is the onboard battery managed for SRAM data retention?\u003c\/strong\u003e\u003c\/p\u003e\n\u003cp\u003eThe onboard Ni-Cd battery is automatically charged whenever the rack is powered. It specifically maintains the voltage for low-power CMOS SRAM circuits during power-down. Note that the retention duration is highly dependent on ambient temperature; cooler environments extend the battery's self-discharge cycle.\u003c\/p\u003e\n\u003cp\u003e\u003cstrong\u003eCan I mix different memory chips in the same group?\u003c\/strong\u003e\u003c\/p\u003e\n\u003cp\u003eMemory groups are mapped in pairs to achieve a 16-bit word length. Therefore, each pair of memory circuits (e.g., two 32 Kbyte chips) must be of the same type and speed to ensure synchronized data processing and prevent bus errors.\u003c\/p\u003e\n\u003cp\u003e\u003cstrong\u003eDoes the board provide built-in voltage monitoring?\u003c\/strong\u003e\u003c\/p\u003e\n\u003cp\u003eThe board does not have onboard voltage supervision; instead, it relies on the\u003cspan\u003e \u003c\/span\u003e\u003cstrong\u003e\/PWF (Power Fail)\u003c\/strong\u003e\u003cspan\u003e \u003c\/span\u003esignal from the system bus. If this signal drops to a \"0\" state, all memory selection signals are inhibited to prevent data corruption during power instability.\u003c\/p\u003e\n\u003chr\u003e\n\u003ch3\u003eEngineering \u0026amp; Installation Guide\u003c\/h3\u003e\n\u003cul class=\"list-paddingleft-2\"\u003e\n\u003cli\u003e\n\u003cp\u003e\u003cstrong\u003eMicroswitch \u0026amp; Jumper Calibration:\u003c\/strong\u003e\u003cspan\u003e \u003c\/span\u003eBefore installation, you must verify the microswitch settings (S23, S25, S27) for the three I\/O address areas. Because this board replaces three separate legacy boards, incorrect switch positions will lead to address conflicts on the DRC backplane.\u003c\/p\u003e\n\u003c\/li\u003e\n\u003cli\u003e\n\u003cp\u003e\u003cstrong\u003eMemory Mapping Logic:\u003c\/strong\u003e\u003cspan\u003e \u003c\/span\u003eAddress areas are separated by the most significant address bit (A14). Ensure that successive map addresses have their A14 bits in different states to avoid selecting the same physical circuit for two different software maps.\u003c\/p\u003e\n\u003c\/li\u003e\n\u003cli\u003e\n\u003cp\u003e\u003cstrong\u003eThermal Management:\u003c\/strong\u003e\u003cspan\u003e \u003c\/span\u003eFor systems utilizing the battery-backed SRAM for critical data, maintain the enclosure temperature below 40 deg C whenever possible.\u003cspan\u003e \u003c\/span\u003e\u003cspan class=\"citation-25 citation-end-25\"\u003eHigh ambient temperatures significantly accelerate the self-discharge rate of the Ni-Cd battery and reduce its overall service life.\u003c\/span\u003e\u003c\/p\u003e\n\u003c\/li\u003e\n\u003cli\u003e\n\u003cp\u003e\u003cstrong\u003eFirmware Replacement:\u003c\/strong\u003e\u003cspan\u003e \u003c\/span\u003eWhen replacing EPROMs (firmware), ensure the chips are seated with the correct orientation in the sockets. Standard 27256 EPROMs should be handled using ESD-safe tools to prevent latent gate damage.\u003c\/p\u003e\n\u003c\/li\u003e\n\u003c\/ul\u003e","brand":"ABB","offers":[{"title":"Default Title","offer_id":52701958635883,"sku":"MEM86-3X192K","price":100.0,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0953\/3227\/0443\/files\/mem86-3x192k-obo2qe44n5n_c13485e8-000f-4ad7-b34e-101fd9043628.jpg?v=1766478159","url":"https:\/\/www.plcprotech.com\/products\/abb-stromberg-mem86-3x192k-programmable-memory-board","provider":"PLC ProTech Ltd.","version":"1.0","type":"link"}