{"product_id":"ge-fanuc-ic693cpu341-series-90-30-cpu-module","title":"GE Fanuc IC693CPU341 Series 90-30 CPU Module","description":"\u003ch3\u003eDescription\u003c\/h3\u003e\n\u003cp style=\"color: #2d3748; margin-bottom: 16px;\"\u003eThe \u003cstrong\u003eGE Fanuc IC693CPU341\u003c\/strong\u003e is a single-slot central processing unit module designed for the Series 90-30 programmable logic controller platform. Driven by an 80C188XL processor operating at a clock speed of 20 MegaHertz, this module provides reliable execution of user logic configurations with a typical scan rate of 0.3 milliseconds per 1K of boolean logic. The architecture supports standard system memory structures alongside flexible volatile and non-volatile storage deployment options across multiple baseplate variants. Equipped with integrated communication path channeling through the power supply interface, it serves as a core processing hub tailored for standard machine automation, distributed assembly architecture, and high-speed process monitoring applications.\u003c\/p\u003e\n\n\u003ch3\u003eFeatures\u003c\/h3\u003e\n\u003cul style=\"list-style-type: square; color: #2d3748; padding-left: 20px; margin-bottom: 16px;\"\u003e\n  \u003cli\u003e\n\u003cstrong\u003eVersatile Storage Implementation:\u003c\/strong\u003e Accommodates standard RAM memory architecture supplemented by option-specific EPROM or EEPROM configurations in historical models.\u003c\/li\u003e\n  \u003cli\u003e\n\u003cstrong\u003eEnhanced Memory Safeguards:\u003c\/strong\u003e Provides transition support for volatile RAM backup alongside direct non-volatile storage utilizing specialized Flash memory structures from hardware iteration J and firmware version 4.61 onward.\u003c\/li\u003e\n  \u003cli\u003e\n\u003cstrong\u003eIntegrated Serial Connectivity:\u003c\/strong\u003e Features one built-in physical communication port utilizing the dedicated linkage channel residing directly on the standard PLC power supply framework.\u003c\/li\u003e\n  \u003cli\u003e\n\u003cstrong\u003eNative Slave Protocols:\u003c\/strong\u003e Deliver operational support for standard SNP and SNP-X serial communication slave interactions right out of the box.\u003c\/li\u003e\n  \u003cli\u003e\n\u003cstrong\u003eExtensive Option Capabilities:\u003c\/strong\u003e Interfaces directly with modular coprocessors including PCM and CMM assemblies to establish native RTU master\/slave, CCM, and SNP\/SNP-X master network control loops.\u003c\/li\u003e\n  \u003cli\u003e\n\u003cstrong\u003eAdvanced Logical Controls:\u003c\/strong\u003e Furnishes active run-time control mechanisms including real-time logical overrides, discrete software interrupts, and a fully battery-backed real-time system clock.\u003c\/li\u003e\n\u003c\/ul\u003e\n\n\u003ch3\u003eApplications\u003c\/h3\u003e\n\u003cul style=\"list-style-type: square; color: #2d3748; padding-left: 20px; margin-bottom: 16px;\"\u003e\n  \u003cli\u003e\n\u003cstrong\u003eMulti-Baseplate Automation Layouts:\u003c\/strong\u003e Centralized coordination across expanded physical I\/O control structures spanning up to five total baseplate sub-assemblies.\u003c\/li\u003e\n  \u003cli\u003e\n\u003cstrong\u003eIndustrial Network Communications:\u003c\/strong\u003e High-density data concentration and routing across multi-drop local area networks, open Ethernet loops, Profibus segments, and FIP bus installations using auxiliary option modules.\u003c\/li\u003e\n  \u003cli\u003e\n\u003cstrong\u003eDiscrete Manufacturing Controls:\u003c\/strong\u003e High-speed tracking and component execution across automated packaging lines, multi-tier conveyer paths, and localized machine tool cells.\u003c\/li\u003e\n\u003c\/ul\u003e\n\n\u003ch3\u003eTechnical Specifications\u003c\/h3\u003e\n\u003cdiv style=\"overflow-x: auto; margin-bottom: 16px;\"\u003e\n  \u003ctable style=\"width: 100%; border-collapse: collapse; color: #2d3748; text-align: left;\"\u003e\n    \u003cthead\u003e\n      \u003ctr style=\"border-bottom: 2px solid #1a365d;\"\u003e\n        \u003cth style=\"padding: 8px; color: #1a365d;\"\u003eParameter\u003c\/th\u003e\n        \u003cth style=\"padding: 8px; color: #1a365d;\"\u003eValue \/ Specification\u003c\/th\u003e\n      \u003c\/tr\u003e\n    \u003c\/thead\u003e\n    \u003ctbody\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003eManufacturer\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003eGE Fanuc (Automation)\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003eCountry of Origin\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003eUnited States\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003eCPU Module Type\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003eSingle slot CPU module\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003eProcessor Architecture\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003e80C188XL\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003eProcessor Speed\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003e20 MegaHertz\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003eTypical Logic Scan Rate\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003e0.3 milliseconds per 1K of logic (boolean contacts)\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003eUser Program Memory (Maximum)\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003e80K Bytes\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003eTotal Baseplates Supported\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003e5 total (1 local CPU baseplate plus up to 4 expansion and\/or remote baseplates)\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003ePower Supply Current Load Requirement\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003e490 milliamps from +5 VDC internal supply\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003eDiscrete Input Allocation (%I)\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003e512 points\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003eDiscrete Output Allocation (%Q)\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003e512 points\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003eDiscrete Global Memory (%G)\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003e1280 bits\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003eInternal Coils (%M)\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003e1024 bits\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003eTemporary Output Coils (%T)\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003e256 bits\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003eSystem Status References (%S)\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003e128 bits total (%S, %SA, %SB, %SC partitioned as 32 bits each)\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003eRegister Memory Configuration (%R)\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003e9999 words\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003eAnalog Inputs (%AI)\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003e1024 words\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003eAnalog Outputs (%AQ)\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003e256 words\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003eSystem Registers (%SR)\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003e16 words (intended for reference data viewing only; restricted from user logic references)\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003eTimers and Counters\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003eGreater than 2000\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003eShift Registers Supported\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003eYes\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003eOperating Temperature Limits\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003e0 to 60 degC (32 to 140 degF) ambient\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003ePCM\/CCM Compatibility\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003eYes\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003eShipping Weight (Calculated)\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003e0.45 kg (0.99 lbs)\u003c\/td\u003e\n      \u003c\/tr\u003e\n      \u003ctr style=\"border-bottom: 1px solid #e2e8f0;\"\u003e\n        \u003ctd style=\"padding: 8px; font-weight: bold;\"\u003ePackage Dimensions (Calculated)\u003c\/td\u003e\n        \u003ctd style=\"padding: 8px;\"\u003e180 mm x 140 mm x 40 mm\u003c\/td\u003e\n      \u003c\/tr\u003e\n    \u003c\/tbody\u003e\n  \u003c\/table\u003e\n\u003c\/div\u003e\n\n\u003ch3\u003eInstallation Guidelines\u003c\/h3\u003e\n\u003cdiv style=\"background-color: #fff5f5; border-left: 4px solid #c53030; padding: 12px; margin-bottom: 16px;\"\u003e\n  \u003cstrong style=\"color: #9b2c2c;\"\u003eCRITICAL WARNING:\u003c\/strong\u003e\n  \u003cp style=\"color: #9b2c2c; margin: 4px 0 0 0;\"\u003eIsolate and disconnect all active input power sources routing to the main PLC baseplate assembly before inserting, extracting, or shifting any module component. Failure to completely de-energize the system power supply rack prior to hardware handling can initiate severe electrical arcing, disrupt internal register memory arrays, or cause permanent functional destruction of the CPU circuitry.\u003c\/p\u003e\n\u003c\/div\u003e\n\n\u003cdiv style=\"margin-bottom: 16px; color: #2d3748;\"\u003e\n  \u003cdiv style=\"margin-bottom: 12px; display: flex; align-items: flex-start;\"\u003e\n    \u003cspan style=\"background-color: #2b6cb0; color: #ffffff; border-radius: 50%; min-width: 24px; min-height: 24px; display: flex; align-items: center; justify-content: center; margin-right: 12px; font-weight: bold;\"\u003e1\u003c\/span\u003e\n    \u003cdiv\u003e\n      \u003cstrong\u003eBaseplate Slot Selection and Alignment:\u003c\/strong\u003e Identify the unique, dedicated CPU slot on the primary Series 90-30 baseplate card (typically located immediately to the right of the rack power supply unit). Align the top and bottom structural guide ribs of the module plastic housing with the corresponding structural card tracks.\n    \u003c\/div\u003e\n  \u003c\/div\u003e\n  \u003cdiv style=\"margin-bottom: 12px; display: flex; align-items: flex-start;\"\u003e\n    \u003cspan style=\"background-color: #2b6cb0; color: #ffffff; border-radius: 50%; min-width: 24px; min-height: 24px; display: flex; align-items: center; justify-content: center; margin-right: 12px; font-weight: bold;\"\u003e2\u003c\/span\u003e\n    \u003cdiv\u003e\n      \u003cstrong\u003eMechanical Seating and Connector Engagement:\u003c\/strong\u003e Press the module firmly straight back into the slot location until the rear connector seating blocks snap securely into the backplane pin group. Ensure that the top and bottom mechanical retention levers actuate and lock flat into place.\n    \u003c\/div\u003e\n  \u003c\/div\u003e\n  \u003cdiv style=\"margin-bottom: 12px; display: flex; align-items: flex-start;\"\u003e\n    \u003cspan style=\"background-color: #2b6cb0; color: #ffffff; border-radius: 50%; min-width: 24px; min-height: 24px; display: flex; align-items: center; justify-content: center; margin-right: 12px; font-weight: bold;\"\u003e3\u003c\/span\u003e\n    \u003cdiv\u003e\n      \u003cstrong\u003eSerial Communication Loop Verification:\u003c\/strong\u003e Secure the serial peripheral cable directly to the built-in communication port interface located on the power supply chassis. Ensure that the connection screws are fully snugged manually to establish a stable ground loop for SNP communication.\n    \u003c\/div\u003e\n  \u003c\/div\u003e\n  \u003cdiv style=\"margin-bottom: 12px; display: flex; align-items: flex-start;\"\u003e\n    \u003cspan style=\"background-color: #2b6cb0; color: #ffffff; border-radius: 50%; min-width: 24px; min-height: 24px; display: flex; align-items: center; justify-content: center; margin-right: 12px; font-weight: bold;\"\u003e4\u003c\/span\u003e\n    \u003cdiv\u003e\n      \u003cstrong\u003eInitial Diagnostics and Boot Testing:\u003c\/strong\u003e Apply system power to the rack. Monitor the localized status indicators on the CPU faceplate to verify that the self-test sequence initializes successfully and enters a stable running mode without invoking the system fault contact.\n    \u003c\/div\u003e\n  \u003c\/div\u003e\n\u003c\/div\u003e","brand":"General Electric","offers":[{"title":"Default Title","offer_id":53352229044587,"sku":"IC693CPU341","price":850.0,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0953\/3227\/0443\/files\/IC693CPU341.png?v=1780745527","url":"https:\/\/www.plcprotech.com\/products\/ge-fanuc-ic693cpu341-series-90-30-cpu-module","provider":"PLC ProTech Ltd.","version":"1.0","type":"link"}