{"product_id":"general-electric-ds200ucpbg5afb-mark-v-io-engine-cpu-board","title":"General Electric DS200UCPBG5AFB Mark V IO Engine CPU Board","description":"\u003ch3\u003eDescription\u003c\/h3\u003e\n\u003cp\u003eThe \u003cstrong\u003eDS200UCPBG5AFB\u003c\/strong\u003e functions as an IO Engine CPU board designed by General Electric for the \u003cstrong\u003eMark V\u003c\/strong\u003e control system series. Operating natively as a daughterboard mounted onto a UCIA motherboard within the I\/O cores, the board houses a 486DX processor and an ARCNET driver to manage external communications with various operator interfaces. The \u003cstrong\u003eDS200UCPBG5AFB\u003c\/strong\u003e features one onboard microprocessor, multiple PROM modules, an internal random access memory architecture, and a specialized 7-switch block. Furthermore, the hardware layout incorporates a singular Power Control Module (PCM) daughterboard dedicated exclusively to driving communication loops with FMVED motor controller components. For physical stacking and bus communication, the board interfaces directly with the STCA board through dedicated bus and serial connections.\u003c\/p\u003e\n\u003ch3\u003eFeatures\u003c\/h3\u003e\n\u003cul\u003e\n\u003cli\u003eDriven by a high-performance 486DX microprocessor supported by multiple PROM modules and random access memory.\u003c\/li\u003e\n\u003cli\u003eIncludes 1 dual in-line memory module (DIMM) connector alongside 1 manually configurable switch block containing 7 switches.\u003c\/li\u003e\n\u003cli\u003eUtilizes a standard 34-pin connector interface in addition to a secondary inter-board attachment connector.\u003c\/li\u003e\n\u003cli\u003eFeatures three manually moveable hardware jumpers designated as JP1, JP2, and JP3 for testing and core tuning.\u003c\/li\u003e\n\u003cli\u003eHouses a functional JP2 jumper used to configure the specific 486 local bus speed parameters.\u003c\/li\u003e\n\u003cli\u003eIntegrates a singular PCM (Power Control Module) daughterboard to facilitate direct communication lines with FMVED motor controller components.\u003c\/li\u003e\n\u003cli\u003eOperates in close conjunction with the companion AAHA board within the control core architecture.\u003c\/li\u003e\n\u003cli\u003eBuilt with a standard normal circuit board coating style to protect critical micro-components.\u003c\/li\u003e\n\u003c\/ul\u003e\n\u003ch3\u003eApplications\u003c\/h3\u003e\n\u003cul\u003e\n\u003cli\u003eMark V core control system processing and application execution.\u003c\/li\u003e\n\u003cli\u003eMotor control communication interfaces linked with FMVED motor controllers.\u003c\/li\u003e\n\u003cli\u003eExternal operator interface data routing via integrated ARCNET driver hardware.\u003c\/li\u003e\n\u003cli\u003eStacked I\/O core processing assemblies mounted onto STCA and UCIA motherboards.\u003c\/li\u003e\n\u003c\/ul\u003e\n\u003ch3\u003eTechnical Specifications\u003c\/h3\u003e\n\u003cfigure class=\"table\"\u003e\n\u003ctable\u003e\n\u003cthead\u003e\n\u003ctr\u003e\n\u003cth\u003e\u003cstrong\u003eParameter\u003c\/strong\u003e\u003c\/th\u003e\n\u003cth\u003e\u003cstrong\u003eSpecification\u003c\/strong\u003e\u003c\/th\u003e\n\u003c\/tr\u003e\n\u003c\/thead\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cstrong\u003eManufacturer\u003c\/strong\u003e\u003c\/td\u003e\n\u003ctd\u003eGE General Electric\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cstrong\u003ePart Number\u003c\/strong\u003e\u003c\/td\u003e\n\u003ctd\u003eDS200UCPBG5AFB\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cstrong\u003eSeries\u003c\/strong\u003e\u003c\/td\u003e\n\u003ctd\u003eMark V\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cstrong\u003eFunctional Description\u003c\/strong\u003e\u003c\/td\u003e\n\u003ctd\u003eIO Engine CPU Board\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cstrong\u003eFunctional Acronym\u003c\/strong\u003e\u003c\/td\u003e\n\u003ctd\u003eUCPB\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cstrong\u003ePCB Coating Style\u003c\/strong\u003e\u003c\/td\u003e\n\u003ctd\u003eNormal Coating\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cstrong\u003eFunctional Revision 1\u003c\/strong\u003e\u003c\/td\u003e\n\u003ctd\u003eA\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cstrong\u003eFunctional Revision 2\u003c\/strong\u003e\u003c\/td\u003e\n\u003ctd\u003eF\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cstrong\u003eArtwork Revision\u003c\/strong\u003e\u003c\/td\u003e\n\u003ctd\u003eB\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003c\/tbody\u003e\n\u003c\/table\u003e\n\u003c\/figure\u003e\n\u003ch3\u003eConnections\/Interfaces\u003c\/h3\u003e\n\u003cfigure class=\"table\"\u003e\n\u003ctable\u003e\n\u003cthead\u003e\n\u003ctr\u003e\n\u003cth\u003e\u003cstrong\u003eInterface Port \/ Connector\u003c\/strong\u003e\u003c\/th\u003e\n\u003cth\u003e\u003cstrong\u003eFunction\u003c\/strong\u003e\u003c\/th\u003e\n\u003c\/tr\u003e\n\u003c\/thead\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cstrong\u003eARCNET COREBUS Connector\u003c\/strong\u003e\u003c\/td\u003e\n\u003ctd\u003eInterface line linking to the STCA board for network communication\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cstrong\u003eCOM1 Port\u003c\/strong\u003e\u003c\/td\u003e\n\u003ctd\u003eTerminal interface monitor connection linking to the STCA board\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cstrong\u003eJ1 and J3 Connectors\u003c\/strong\u003e\u003c\/td\u003e\n\u003ctd\u003eMain STCA board bus connections extending to the UCIA motherboard\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cstrong\u003eIDE Connector\u003c\/strong\u003e\u003c\/td\u003e\n\u003ctd\u003eUnused port during normative board functions\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cstrong\u003eCOM2 Connector\u003c\/strong\u003e\u003c\/td\u003e\n\u003ctd\u003eUnused serial port during normative board functions\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003c\/tbody\u003e\n\u003c\/table\u003e\n\u003c\/figure\u003e\n\u003ch3\u003eInstallation Guidelines\u003c\/h3\u003e\n\u003cul\u003e\n\u003cli\u003e\n\u003cstrong\u003eDIMM Swapping:\u003c\/strong\u003e When replacing the board, the DIMM slot on the replacement unit arrives empty from the factory. Carefully extract the existing DIMM from the old board and insert it into the replacement board following original manual guidelines to prevent physical breakage.\u003c\/li\u003e\n\u003cli\u003e\n\u003cstrong\u003eJumper Configuration:\u003c\/strong\u003e Ensure the vestigial jumpers JP1 and JP3 remain untouched as they are reserved for factory testing only. Adjust the customizable JP2 jumper to match the required 486 local bus speed specifications prior to system boot.\u003c\/li\u003e\n\u003cli\u003e\n\u003cstrong\u003eChassis Mounting:\u003c\/strong\u003e Align the connectors J1 and J3 carefully when securing the daughterboard configuration onto the UCIA motherboard and the underlying STCA board assembly to prevent pin distortion.\u003c\/li\u003e\n\u003c\/ul\u003e","brand":"General Electric","offers":[{"title":"Default Title","offer_id":52695410966891,"sku":"DS200UCPBG5AFB","price":100.0,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0953\/3227\/0443\/files\/general-electric-ds200ucpbg5afb-i-o-engine-cpu-board-pedeohhzzqr_4b04617b-6fdb-4a66-93b7-feba49d4c6dc.jpg?v=1766135063","url":"https:\/\/www.plcprotech.com\/products\/general-electric-ds200ucpbg5afb-mark-v-io-engine-cpu-board","provider":"PLC ProTech Ltd.","version":"1.0","type":"link"}