General Electric DS200UCPBG5AFB Mark V IO Engine CPU Board

Description

The DS200UCPBG5AFB functions as an IO Engine CPU board designed by General Electric for the Mark V control system series. Operating natively as a daughterboard mounted onto a UCIA motherboard within the I/O cores, the board houses a 486DX processor and an ARCNET driver to manage external communications with various operator interfaces. The DS200UCPBG5AFB features one onboard microprocessor, multiple PROM modules, an internal random access memory architecture, and a specialized 7-switch block. Furthermore, the hardware layout incorporates a singular Power Control Module (PCM) daughterboard dedicated exclusively to driving communication loops with FMVED motor controller components. For physical stacking and bus communication, the board interfaces directly with the STCA board through dedicated bus and serial connections.

Features

• Driven by a high-performance 486DX microprocessor supported by multiple PROM modules and random access memory.
• Includes 1 dual in-line memory module (DIMM) connector alongside 1 manually configurable switch block containing 7 switches.
• Utilizes a standard 34-pin connector interface in addition to a secondary inter-board attachment connector.
• Features three manually moveable hardware jumpers designated as JP1, JP2, and JP3 for testing and core tuning.
• Houses a functional JP2 jumper used to configure the specific 486 local bus speed parameters.
• Integrates a singular PCM (Power Control Module) daughterboard to facilitate direct communication lines with FMVED motor controller components.
• Operates in close conjunction with the companion AAHA board within the control core architecture.
• Built with a standard normal circuit board coating style to protect critical micro-components.

Applications

• Mark V core control system processing and application execution.
• Motor control communication interfaces linked with FMVED motor controllers.
• External operator interface data routing via integrated ARCNET driver hardware.
• Stacked I/O core processing assemblies mounted onto STCA and UCIA motherboards.

Technical Specifications

Connections/Interfaces

Installation Guidelines

• DIMM Swapping: When replacing the board, the DIMM slot on the replacement unit arrives empty from the factory. Carefully extract the existing DIMM from the old board and insert it into the replacement board following original manual guidelines to prevent physical breakage.
• Jumper Configuration: Ensure the vestigial jumpers JP1 and JP3 remain untouched as they are reserved for factory testing only. Adjust the customizable JP2 jumper to match the required 486 local bus speed specifications prior to system boot.
• Chassis Mounting: Align the connectors J1 and J3 carefully when securing the daughterboard configuration onto the UCIA motherboard and the underlying STCA board assembly to prevent pin distortion.