GH R445 0100 R1 Module synchroniseur Sigma-tronic ABB

Product Overview

The GH R445 0100 R1 (GHR4450100R1), also known as the R 445.1, is a precision synchronizer module from the legacy BBC Brown Boveri Sigma-tronic b system. Engineered as the critical command interface for single and multi-decade up/down counting systems, this module serves as the primary timing controller for R 445.4 and R 445.5 counter stages. Its core function is to synchronize asynchronous control signals—such as count, reset, and direction—into a timed sequence that prevents logic race conditions in multi-digit displays. Whether utilized in legacy power plant monitoring or heavy industrial automation, the GH R445 0100 R1 ensures error-free counting up to 2 kHz, even during high-speed direction switchovers, making it vital for maintaining the integrity of high-precision positioning and measurement data.

Technical Specifications

FAQs

How does the R 445.1 handle counting direction changes at high frequencies?

The module is designed for "error-free" switchover. After a direction change at the VR input, the internal logic pauses pulse processing for approximately 0.5 ms to synchronize all downstream decades. This ensures that no pulses are lost or double-counted during the transition between forward and reverse modes.

What is the purpose of the RM (Feedback) input?

The RM input acts as a mechanical "stop" for the counter. By connecting it to the carry output of the most significant decade, you prevent the counter from rolling over. For example, a 3-digit counter will stop at 999 or 000 rather than resetting to zero or jumping to 999. To disable this feature, the RM input must be tied to a 1-signal (+ Us).

Does this module require external diodes for inductive loads?

No. The Sigma-tronic b R 445.1 outputs are robustly designed to switch inductive loads without the need for external free-wheeling diodes, simplifying the wiring within the control cabinet.

How many counting stages can a single synchronizer module control?

The R 445.1 is rated to drive between 1 and 6 up/down counter decades (R 445.4/5), providing a maximum display capacity of 999,999.

Engineering & Installation Guide

• Signal Synchronization Timing: When designing high-speed control logic, account for the 0.35 ms recovery period required after a Reset (R) or Transfer (ÜS) signal is removed. If a count pulse arrives within this window, it may not be recognized.

• Interference Decoupling: The Transfer Output (QUS) is often used to supply the "preselector set" logic. In complex systems with long wire runs, we recommend implementing interference decoupling or signal amplification at this node to maintain pulse sharp edges and avoid false triggering.

• Inhibit Logic Behavior: The Inhibit Input (S) can be toggled regardless of the state of the Count Input (Z). However, if an inhibit signal is received while a pulse is currently being processed, the module is engineered to complete that specific pulse cycle before halting, ensuring no "half-counts" occur.