B&R X20CP1585 X20 System CPU Controller Module

Technical Overview

The B&R X20CP1585 (X20CP1585) is a high-capacity industrial PLC controller executing on an Intel Atom 333 MHz compatible processor core, engineered for centralized automation control within the standard X20 system topology. Built for complex control routines in CNC machining, automated logistics hubs, and processing plants, this core processing unit coordinates high-speed fieldbus communications to guarantee deterministic cycle times and eliminate unexpected process interruptions. The architecture integrates 128 MB DDR2 RAM alongside 1 MB non-volatile SRAM, utilizing an external CompactFlash card slot for non-volatile application memory. Outfitted with high-speed Ethernet, deterministic POWERLINK, RS232, and dual USB ports, this controller orchestrates real-time distributed IO systems while handling demanding communication metrics safely and reliably.

Technical Configuration

The onboard architecture combines localized control logic with a built-in power supply stage to optimize panel real estate:

• Integrated Communication Stack: Features a native 10/100/1000BASE-T Gigabit Ethernet interface for IT connectivity alongside a dedicated hardware POWERLINK interface for hard real-time, jitter-free motion synchronization.

• Expansion Adaptability: Provides one dedicated expansion slot for X20 interface modules to incorporate legacy fieldbuses or additional specialized communication links.

• Dual Power Infrastructure: Includes a built-in CPU and X2X Link power supply stage operating from a 24 VDC nominal source, providing up to 7 W of output power to downstream IO slices.

• Redundancy Capabilities: The internal X2X Link power supply supports parallel connection configurations, facilitating full redundant power architecture across the IO bus backplane.

Technical Specifications

Industrial Application FAQs

• What occurs if the internal fuse on the CPU power supply trips?

  The CPU and X2X Link power supply section features an integrated, non-replaceable electronic fuse. If an overcurrent event occurs due to a severe internal hardware fault, the fuse opens permanently to protect the remaining backplane modules. The CPU block must then be replaced. Always implement proper external power distribution fuses to prevent this condition.

• How does the controller retain variables and retain data during a power failure?

  The X20CP1585 features 1 MB of high-speed SRAM. Crucial operational metrics, alarm logs, and recipe states designated as retain variables in B&R Automation Studio are automatically written to this non-volatile memory block during controlled or unexpected shutdowns, eliminating the need for an external buffer battery.

• Can the integrated X2X Link power supply run concurrently with another power module?

  Yes. The X2X Link power supply output supports parallel connection and redundant operations. If the downstream IO slices demand more than the native 7 W threshold, or if high-availability redundancy is mandatory, a separate X20 power supply module can be introduced on the bus stack without causing electrical conflicts.

Field Engineering and Installation Directives

POLARITY AND VOLTAGE GUARD: Although the CPU logic circuit features reverse polarity protection, the separate I/O power input does not handle overvoltage conditions elegantly. Always utilize a regulated 24 VDC switch-mode power supply (SMPS) and install a maximum 10 A slow-blow line fuse upstream of the I/O power terminals to guard the internal contacts.

Memory Card Handshaking

Never remove or insert the CompactFlash application memory card while the PLC status LEDs indicate active CPU operations or run execution modes. Doing so will corrupt the file system and abort running processes. Power down the 24 VDC supply completely before swapping or extracting the memory card.

Bus Termination and Grounding

The controller must be bracketed by the standard X20TB12 terminal block and capped on the right-hand side using the included X20AC0SR1 end cover plate. The end plate provides the necessary mechanical stability and electrical termination for the high-speed X2X backplane bus, preventing data transmission reflections and maintaining electromagnetic shielding integrity.